This invention relates generally to semiconductor integrated circuit technique and more specifically, to semiconductor integrated circuit technique which will be particularly effective when applied to an inspection system of a delay time of a semiconductor integrated circuit. Further, the present invention relates to technique which will be effective when utilized for a semiconductor integrated circuit having memories and logic circuits, for example, embedded therein.
To evaluate a semiconductor chip by measuring a delay time, etc., of a circuit or circuits inside a semiconductor integrated circuit device, it has been a customary practice to generate a timing signal for the test by an external testing equipment (such as a tester) and to apply the signal to the semiconductor integrated circuit device. However, if all the timing signals necessary for testing the semiconductor integrated circuit device are generated by the external testing equipment, a load to the testing equipment increases and the cost of such equipment becomes high. Further, if the test is carried out by the use of the timing signals generated primarily by the external testing equipment, wrong diagnosis might occur because characteristics of internal devices of the semiconductor integrated circuit device change depending on temperatures, and so forth.
Therefore, a technique which embeds a test timing generation circuit for generating the timing signals for the test into the chip has been proposed (U.S. Pat. No. 4,608,669 corresponding to JP-A-60-245275) in order to correctly judge whether or not memory arrays inside the semiconductor integrated circuit device are in match with the specification of timing and to reduce the load to the testing equipment.
The technique of measuring a delay time of a certain circuit inside an LSI chip is described in U.S. Pat. Nos. 4,489,272 and 4,392,105.
When the test timing generation circuit is embedded into the semiconductor integrated circuit device, the test timing signal generated by this test timing generation circuit, too, are affected by variance in a fabrication process and by the condition of use of the semiconductor integrated circuit device. Therefore, timing of the signals so generated must be measured by an external tester.
However, the delay time of circuits has become shorter and shorter in recent years with the progress of semiconductor fabrication technique, and the tester for measuring the delay time of the circuits must have higher accuracy. Nonetheless, the testing equipment for evaluating new high speed products fabricated by the latest process technique is constituted by using lower speed semiconductor devices fabricated by more obsolete technique. For this reason, accuracy accomplished by the testing equipment is not sufficient in some cases in comparison with the object of the test. Accordingly, the conventional semiconductor integrated circuit devices are often found defective only after they are used in practice.
The test of the semiconductor integrated circuit devices is carried out in many cases using a prober under a wafer state where they are not yet diced. However, in comparison with the test which is carried out after the semiconductor integrated circuit device is assembled into a package, the wiring length from the semiconductor integrated circuit device to the testing equipment is greater in the probing test and hence, a greater impedance is applied to the semiconductor integrated circuit device. This invites the drop of measurement accuracy of test timing. Accordingly, there is also the case where the semiconductor integrated circuit device is found defective by the test after it is assembled into the package. In other words, since the package assembly work, which is originally not necessary, is carried out in vain, the cost of production becomes higher.